FPGA U-Net Accelerator
Real-time semantic segmentation on a Zybo Z7-20 at under 3 W.
Final year project: a hardware-software co-design that trains a custom lightweight U-Net, quantizes it to INT8 and deploys it on a Zynq-7000 FPGA for autonomous-driving scene segmentation. The model shrinks 56 times to 570 KB so it fits in on-chip BRAM, while keeping 97% pixel accuracy on the CARLA dataset. The RTL is fully verified and the whole pipeline, from PyTorch training to bitstream, is documented.
This repository is private.
The write-up above covers what can be shared publicly. Happy to walk through the code and results on a call, just get in touch.
More in FPGA
Related projects
FPGA20255-Stage Pipelined RISC-V Processor
RV32I core with hazard detection and forwarding, running at 100 MHz on Artix-7.
- SystemVerilog
- Vivado
- Nexys A7
- Assembly
Private repoFPGA2026AI Accelerator: Co-Design Pipeline
The step-by-step hardware-software flow behind the U-Net accelerator on Zybo Z7-20.
- SystemVerilog
- Vitis HLS
- Vivado
- C
- SystemVerilog
- Vivado
- Nexys A7
- Assembly