FPGA & Digital Design2026 Private repo
AI Accelerator: Co-Design Pipeline
The step-by-step hardware-software flow behind the U-Net accelerator on Zybo Z7-20.
The engineering companion to the FPGA U-Net accelerator: environment setup, model export, HLS and RTL blocks, and the ARM Cortex-A9 processing-system side of the Zynq-7000 that feeds the programmable logic. Written as a guide so the flow can be reproduced.
This repository is private.
The write-up above covers what can be shared publicly. Happy to walk through the code and results on a call, just get in touch.
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