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Awais Asghar.
FPGA & Digital Design2025

FPGA Smart Car Security System

A concealed, reprogrammable anti-theft FSM with siren and fuel-pump interlock.

Designed on the DE1-SoC in Verilog and SystemVerilog: a reprogrammable finite state machine detects unauthorized entry, debounces sensor inputs, generates a siren and cuts the fuel pump. Timers and debouncers were verified glitch-free in simulation.

Source on GitHub
FPGA Smart Car Security System thumbnail

README · rendered from GitHub

FPGA-Based-Smart-Car-Security-System

Project Status Platform Tool-Vivado Tool-Quartus Simulator Language-Verilog Language-SystemVerilog

Introduction

A concealed and reprogrammable smart anti-theft system designed using Verilog HDL and system verilog for high-end vehicles such as Porsche. This project enhances security by detecting unauthorized access, activating an audible alarm, and securely disabling the fuel pump unless the correct hidden owner-authenticated sequence is performed.

Overview

Overview

Requirements

How the System Works

Think of the system like a guard dog that: o Sleeps quietly until you leave the house. o Starts watching when the house is empty. o If someone opens the door, it gives them a few seconds — if they don’t prove they belong, it starts barking (alarm). o And secretly, it locks the fuel line so even if the thief stops the barking, the car won’t move.

Major Features

Features

System Diagram

System Diagram

Block Diagram

Block Diagram

FSM Diagram

FSM 1 FSM 2

Timing Parameters

Timing Parameters

These values are stored in memory and can be reprogrammed at runtime.

Tools and Technologies

  • HDL: Verilog / SystemVerilog
  • Simulation Tool: ModelSim-Altera Edition
  • Synthesis Tool: Quartus / Vivado
  • Waveform Viewer: GTKWave
  • Editor: Visual Studio Code (VS Code)
  • Version Control: Git
  • Target FPGA Board: DE1-SoC (Intel/Altera)

Modules Hierarchy

Module Names

RTL Design and Simulation of Testbenches

Car Anti Theft Alarm System (Top module)

Top module Image Testbench

Anti-Theft FSM

Anti Theft FSM Image

Fuel Pump Logic

Fuel Pump Logic Image Testbench

Siren Generator

Siren Generator Image Testbench

Time Parameters

Time Parameters Image Testbench

Timer 1Hz

Timer 1Hz Image

Time Parameters With Reprogrammability

Time Parameters With Reprogrammability Image Testbench

Debouncer

Debouncer Image

Implementation

Image

Simulation Checklist

  • FSM Behavior: Verified transitions between all states (Armed, Triggered, Alarm, Disarmed)
  • Timer Accuracy: All time intervals matched expected durations
  • Siren Modulation: Alternating 440Hz and 880Hz tones confirmed
  • Fuel Pump Lock: Disarm sequence required to restore pump power
  • LED Indicator: Correct status signal behavior (blinking, solid, off)
  • Debouncer: Inputs free from glitches or spurious toggles
  • Time Reprogrammability: Parameters updated and reflected immediately
  • Testbenches: Each module tested independently in ModelSim Altera

Results

Below are key results verified from simulations and waveform analyses:

  • Auto-Arming Delay: System enters Armed state exactly 6 seconds after ignition off and all doors closed.
  • Driver Door Trigger: Countdown of 8 seconds starts upon driver door open. LED solid during countdown.
  • Siren Behavior: Siren asserts if countdown expires, alternating tones confirmed via waveform.
  • Fuel Pump Safety: Fuel pump remains OFF until brake + hidden switch are pressed under ignition.
  • Parameter Update: New values loaded during reprogramming reflected instantly in next FSM cycle.
  • No Metastability: Debouncer module ensures all transitions are clean and glitch-free.
  • FSM Coverage: All FSM transitions including resets, armed/triggered/alarm/disarm verified.

Real-Life Scenarios

Case 1 Case 2

Future Work

Future Work

License

This project is licensed under the MIT License.

Regards

Regards

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